Organic thin film transistor and manufacturing method thereof

ABSTRACT

There is provided an organic thin film transistor comprising: an organic substrate; a gate electrode; a gate insulating film; an organic semiconductor film; a source electrode; and a drain electrode, and in the organic thin film transistor, an average surface roughness Ra of the gate electrode which is in contact with the gate insulating film is 0.1 nm to 15 nm. The organic thin film transistor provides a stable performance characteristic even when a conductor film provided on a substrate whose shape is unstable and whose flatness is low as compared with a silicon wafer, such as a substrate made of a glass epoxy resin, is used as a gate electrode.

TECHNICAL FIELD

The present invention relates to an organic thin film transistor usingan organic semiconductor material and a method of manufacturing theorganic thin film transistor.

BACKGROUND ART

In recent years, a development race of a thin film transistor using anorganic semiconductor material (hereinafter referred to as “organic thinfilm transistor”) is accelerating. By using the organic material, aprocess temperature is reduced. Therefore, it is expected thattransistors can be formed on a large area at low cost. It is anticipatedthat organic thin film transistors will be applied to a drive circuitfor a thin display and an electronic paper, a radio frequencyidentification (RF-ID) tag, an IC card, and the like. There are severaltechnical reviews (see for example, C. D. Dimitrakopoulos, et al.“Organic Thin Film Transistors for Large Area Electronics”, AdvancedMaterial, 2002, 14, No. 2, pp. 99-117).

FIG. 3 shows a structural example of an organic thin film transistor.Reference numeral 301 denotes a substrate; 302, a gate electrode madefrom a conductor film; 303, a gate insulating film; 304, an organicsemiconductor film; 305, a source electrode; and 306, a drain electrode.

In FIG. 3, for example, a glass epoxy resin can be used for thesubstrate 301. In this case, with respect to the gate electrode 302, theconductor film is patterned in a gate electrode shape and then subjectedto a planarization process by polishing. The gate insulating film, theorganic semiconductor film, the source electrode, and the drainelectrode are formed on the processed conductor film, thereby composingthe organic thin film transistor.

In order to operate the organic thin film transistor, a voltage thatexceeds a threshold voltage Vth is applied to the gate electrode in astate in which the source electrode is grounded and a drain voltage Vddis applied to the drain electrode. At this time, a conductivity of theorganic thin film transistor is changed by an electric field from thegate electrode, so that a current flows between the source electrode andthe drain electrode. Therefore, as in a switch, the on-and-off controlof the current flowing between the source electrode and the drainelectrode can be performed according to the gate voltage.

Up to now, a large number of examples in which an organic thin filmtransistor is formed using a substrate made of a material other than anSi wafer have been reported. However, there are few examples in whichmobility exceeds 0.1 cm²/Vs. For example, there is a report thatmobility exceeds 1 cm²/Vs when a transistor is formed on an Si waferusing pentacene for an organic semiconductor film. However, even if thesame pentacene is used, when a transistor is formed on a PET, themaximum mobility is about 0.05 cm²/Vs. There is a report that mobilityis 0.2 cm²/Vs when a transistor is formed on a polycarbonate. This is anexceptional case because a high dielectric constant material is used fora gate insulating film (see for example, C. D. Dimitrakopoulos, et al.“Low-Voltage Organic Transistors on Plastic Comprising High-DielectricConstant Gate Insulators”, Science, 1999, 283, p. 822). It isconceivable that a substrate surface roughness is one of the factorsreducing the mobility even in the case of using the same material.

In producing the organic thin film transistor having the structure shownin FIG. 3, the flatness of the surface of the gate electrode isimportant. In particular, there is a problem in the case where anorganic polymer material such as polyethylene terephthalate orpolycarbonate having lower flatness than a silicon wafer is used for asubstrate, or in the case where a glass epoxy resin to which a copperfoil is added is used for a printed substrate. Because the surfaceroughness is 10 times to 1000 times larger than that of the siliconwafer, a coverage of the gate insulating film formed on the gateelectrode is bad at some locations to increase a gate leakage.Therefore, a sufficient electric field effect is not obtained. Inaddition, a variation in film thickness of the gate insulating film iscaused at some locations, so that this becomes a factor varyingtransistor characteristics. Further, in some cases, the mobility isreduced due to the surface roughness.

When an organic thin film transistor having stable operatingcharacteristics is produced by using a substrate other than the siliconwafer, a process for planarizing the surface of the gate electrode onwhich the gate insulating film is formed is required. As a planarizingprocess, there has been widely known chemical mechanical polishing (CMP)for planarizing the insulating film to realize a multi-layer wiring insilicon technology. However, in a method of directly forming atransistor on a substrate whose shape is unstable and whose flatness islow as compared with the silicon wafer, such as a substrate made of aglass epoxy resin, sufficient findings to the surface roughness requiredon the surface of the gate electrode are not obtained.

DISCLOSURE OF THE INVENTION

An object of the present invention is to define a planarization levelrequired to obtain a stable transistor operation in the case where asurface of a gate electrode is planarized by a polishing process.

Another object of the present invention is to provide a technique ofusing as a gate electrode a conductor film provided on a substrate whoseshape is unstable and whose flatness is low as compared with a siliconwafer, such as a substrate made of a glass epoxy resin.

Still another object of the present invention is to provide a low costsemiconductor device using a large number of transistors in which stableoperating characteristics are obtained.

After concentrated studies were conducted with respect to the presentinvention, it is concluded that the following structures are suitable.

That is, according to the present invention, there is provided anorganic thin film transistor comprising: an organic substrate; a gateelectrode; a gate insulating film; an organic semiconductor film; asource electrode; and a drain electrode, in which an average surfaceroughness Ra of the gate electrode which is in contact with the gateinsulating film is 0.1 nm to 15 nm.

It is preferable that the organic substrate is made of one of a glassepoxy resin, polyethylene terephthalate, and polyimide.

Further, according to the present invention, there is provided a methodof manufacturing an organic thin film transistor which comprises anorganic substrate, a gate electrode, a gate insulating film, an organicsemiconductor film, a source electrode, and a drain electrode, themethod comprises the steps of: preparing an organic substrate in which aplanarized gate electrode is formed on a surface thereof; and forming agate insulating film on the planarized gate electrode, in which anaverage surface roughness Ra of the planarized gate electrode is 0.1 nmto 15 nm.

It is preferable that the organic substrate is made of one of a glassepoxy resin, polyethylene terephthalate, and polyimide.

Further, it is preferable that the planarized gate electrode is formedby sputtering, or that the method of manufacturing an organic thin filmtransistor further includes planarizing the gate electrode.

Further, it is preferable that in planarizing, at least one of chemicalmechanical polishing (CMP), soft etching, and polishing tape processingis performed.

According to the present invention, in the organic thin film transistorusing the organic semiconductor film, an average surface roughness Ra onthe surface of the gate electrode which is in contact with the gateinsulating layer is set to a range of 0.1 nm to 15 nm. Therefore, it ispossible to use as the gate electrode a conductor film provided on asubstrate whose shape is unstable and whose flatness is low as comparedwith a silicon wafer, such as a substrate made of a glass epoxy resin.

Also, it is possible to obtain a low cost semiconductor device using alarge number of transistors in which stable operating characteristics.

Other features and advantages of the present invention will be apparentfrom the following description taken in conjunction with theaccompanying drawings, in which like reference characters designate thesame or similar parts throughout the figures thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate embodiments of the invention and,together with the description, serve to explain the principles of theinvention.

FIG. 1 is a schematic view showing a structure of an organic thin filmtransistor according to the present invention.

FIG. 2 is an AFM image of a thin film composing a gate electrode usedfor the organic thin film transistor according to the present invention.

FIG. 3 is a schematic view showing a structure of a conventional organicthin film transistor.

FIG. 4 is a schematic view showing the process of producing the organicthin film transistor according to the present invention.

FIG. 5 is a schematic view showing the process of producing the organicthin film transistor according to the present invention.

FIG. 6 is a schematic view showing the process of producing the organicthin film transistor according to the present invention.

FIG. 7 is a schematic view showing the process of producing the organicthin film transistor according to the present invention.

FIG. 8 is a schematic view showing the process of producing the organicthin film transistor according to the present invention.

FIG. 9 is an AFM image of a thin film composing a gate electrode in acomparative example.

FIG. 10 is a graph showing a measurement result in the case where asubstrate (produced by Toray Industries, Inc.) is used and no processingis performed in Example 3 of the present invention.

FIG. 11 is a graph showing a measurement result in the case of softetching processing in Example 3 of the present invention.

FIG. 12 is a graph showing a measurement result in the case of CMP inExample 3 of the present invention.

FIG. 13 is a graph showing a measurement result in the case of tapeprocessing in Example 3 of the present invention.

FIG. 14 is a graph showing a measurement result in the case of CMP inExample 3 of the present invention.

FIG. 15 is a graph showing a measurement result in Example 4 of thepresent invention.

FIG. 16 is a graph showing a measurement result on a UPISEL D substrateproduced by UBE Industries, Ltd. in Example 4 of the present invention.

FIG. 17 is a graph showing results in Example 3 and Example 4 of thepresent invention.

BEST MODES FOR CARRYING OUT THE INVENTION

Preferred embodiments of the present invention will now be described indetail in accordance with the accompanying drawings.

Concentrated studies were conducted with respect to the flatness on asurface of a gate electrode which is suitably used for producing atransistor on a substrate whose shape is unstable and whose flatness islow, such as a substrate made of a glass epoxy resin. From the studies,it has been found effective to set an average surface roughness Ra onthe surface of the gate electrode to a range of 0.1 nm to 15 nm. Thatis, the following is found. Even if the surface roughness beforepolishing is a level outside the range, if processing is performed suchthat the surface roughness falls within this range after polishing,sufficient transistor characteristics can be obtained. Alternatively, bypreparing a substrate including a flat gate electrode in which thesurface roughness falls within the range, the sufficient transistorcharacteristics can be obtained. The present invention has been madebased on the findings.

In the present invention, an average surface roughness Ra is defined bya mean roughness (Ra) described in Digital Instruments NanoScope III,offline menu manual Ver. 4.4.

According to this description, a three-dimensional average roughnesswith respect to a center plane is defined by the following Expression(1), $\begin{matrix}{{Ra} - \frac{\sum{{{Zi} - {Zcp}}}}{N}} & (1)\end{matrix}$where N: the number of data points

Zi: value of Z at each of the data point

Zcp: value of Z on center plane.

The center plane indicates a plane which is located such that a volumeproduced from a region surrounded by the center plane and a surfaceshape in the front side of the center plane becomes equal to that in therear side thereof which is opposed to the front side.

The JIS of a roughness estimation index to a three-dimensional surfaceform is not provided like in the case of a two-dimensional surface form.Even in the case of a surface shape observing apparatus using a whiteinterferometer (Zygo product or the like) or a surface shape observingapparatus using laser light, an index written by Ra is proposed fromvarious companies. There is no situation that the indexes Ra obtained bymeasuring the same surface of the same sample using differentmeasurement units are always identical. However, even when a measurementmethod is changed, substantially identical numerical values areobtained, so that a function in the case where Ra is used as an index issatisfied. In addition, the index is compatible with an arithmeticaverage roughness Ra defined by JIS B-0601.

FIG. 1 shows a structural example of an organic thin film transistoraccording to the present invention. Reference numeral 101 denotes asubstrate; 102, a gate electrode made from a conductor film; 103, a gateinsulating film; 104, an organic semiconductor film; 105, a sourceelectrode; and 106, a drain electrode.

As compared with FIG. 3, FIG. 1 according to the embodiment of thepresent invention emphasizes a state in which the surface roughnesses ofthe gate electrode, the gate insulating film, and the organicsemiconductor film in a channel region located between the sourceelectrode and the drain electrode are large. A polishing condition ofthe gate electrode is appropriately set to define a necessary flatnesslevel. Therefore, it is possible to produce an organic thin filmtransistor using a low cost substrate.

The operational order of the organic thin film transistor according tothe present invention is the same as in the conventional transistorshown in FIG. 3. That is, a voltage that exceeds a threshold voltage Vthis applied to the gate electrode in a state in which the sourceelectrode is grounded and a drain voltage Vdd is applied to the drainelectrode. At this time, the conductivity of the organic thin filmtransistor is changed by an electric field from the gate electrode, sothat a current flows between the source electrode and the drainelectrode. Therefore, as in a switch, the on-and-off control of thecurrent flowing between the source electrode and the drain electrode canbe performed according to the gate voltage.

The surface roughness of a copper foil bonded to the glass epoxy resinsubstrate on which polishing is not performed is about 1 μm. The averagesurface roughness Ra of the copper foil falls within a range of 0.1 nmto 15 nm by a CPM, thereby obtaining sufficient characteristics. It ispossible to reduce Ra to a value smaller than 0.1 nm. However, thisreduction targets a surface roughness superior to that of the siliconwafer. Therefore, polishing requires a lot of time, so that the merit inthe case where the glass epoxy resin substrate is used is lost in cost.In addition, it is necessary to increase a film thickness of theconductor film before polishing. On the other hand, when the organicthin film transistor is produced in a state in which Ra exceeds 15 nm, agate leakage is frequently caused, thereby impairing the reliability. Inaddition, the mobility cannot be increased. Therefore, when an organicthin film transistor is formed using a substrate other than a siliconwafer, it is desirable that the average surface roughness Ra specifiedby the embodiment of the present invention is set to a range of 0.1 nmto 15 nm. Further, to increase the merit in terms of cost, it isdesirable that the average surface roughness Ra is set to a range of 1nm to 10 nm. When the reliability is further improved to obtain themerit in terms of cost, it is most desirable that the average surfaceroughness Ra is set to a range of 1 nm to 5 nm.

An organic substrate according to the embodiment of the presentinvention can be selected from a substrate made of a polymer materialsuch as polyethylene terephthalate, polycarbonate, polyethylene,polystyrene, polyimide, polyvinyl acetate, polyvinyl chloride, orpolyvinylidene chloride, a glass epoxy resin substrate used for aprinted circuit board, and the like. It is possible to suitably select asubstrate according to usage from the viewpoint of items required forthe substrate, such as flatness, strength, heat resistance, thermalexpansion coefficient, and cost.

A material of the organic semiconductor film according to the embodimentof the present invention can be selected as appropriate from an oligomerhaving a n conjugated electron, such as pentacene, tetracene, oranthracene, an organic semiconductor polymer such as polythiophene,polyacene, polyacetylene, or polyaniline.

An inorganic oxide such as SiO₂, Al₂O₃, or Ta₂O₅, or a nitride such asSi₃N₄ can be used for the gate insulating film according to theembodiment of the present invention. When an on-resistance is reduced toincrease a drain current, it is preferable that the gate insulating filmis made of a high dielectric constant material. In addition, aninsulating organic polymer such as polyvinylphenol (PVP), polymethylmethacrylate (PMMA), or polyethylene can be used.

A noble metal such as gold, silver, or platinum, or a high conductivitymaterial such as copper or aluminum can be used for the gate electrode,the source electrode, and the drain electrode according to theembodiment of the present invention. In addition, these electrodes canbe formed using a conductive polymer.

The essence of the present invention is to define the surface roughnesson the surface of the gate insulating film which is in contact with theorganic semiconductor film, which is required to stably operate theorganic thin film transistor. Therefore, needless to say, it is possibleto technically arrange a polishing method, which can be made by variousengineers in the field. An object to be polished may be the gateinsulating film, the gate electrode, or the substrate. A state of thesurface of the gate insulating film, which is in contact with theorganic semiconductor film is absolutely important. However, when thegate insulating film is polished, the thickness of the gate insulatingfilm changes according to locations. Therefore, the conditions of anelectric field change or the insulation property is impaired. Thus,according to a most preferable aspect, the gate electrode becomes apolishing object.

Hereinafter, the present invention will be specifically described bygiving examples.

EXAMPLE 1

FIGS. 4 to 8 are schematic views showing a method of producing theorganic thin film transistor according to the present invention. In FIG.4, reference numeral 401 denotes a substrate and 402 denotes a conductorfilm. With respect to the substrate 401 and the conductor film 402, forexample, a glass epoxy resin substrate which is integrally formed with acopper foil is commercially available as a printed circuit board. Inthis example, a substrate having a thickness of 0.2 mm in which a filmthickness of the copper foil serving as the conductor film was 35 μm wasused (produced by Hitachi Chemical Co., Ltd.; type: FR-4). A largenumber of substrates, each of which had a structure in which theconductor film was provided on both surfaces of the substrate. However,the conductor film provided on one surface is unnecessary on thedescription of the present invention and thus omitted here. The samereference numerals in FIGS. 4 to 8 indicate the same members.

Next, the conductor film was patterned to process it in a desirable gateshape. For this processing, it is possible to perform a mask formationby a lithography technique using a dry film and a shape transfer by wetetching on the conductor film. FIG. 5 shows a state in which theconductor film has been processed in a wiring shape. Reference numeral402 denotes a conductor film which becomes the gate electrode. After wetetching, the conductor film 402 was polished by a CMP to adjust to asurface roughness required to embody the present invention.

FIG. 6 shows a state in which a gate insulating film 403 was formed onthe conductor film 402 which becomes the gate electrode. The gateinsulating film 403 was formed using magnetron sputtering system. A filmformation region of the gate insulating film 403 was specified by ashadow mask. A sputtering material was Al₂O₃. A film thickness of thegate insulating film 403 was 250 nm.

FIG. 7 shows a state in which an organic semiconductor film 404 wasformed on the gate insulating film 403. The organic semiconductor film404 was formed using evaporation. A film formation region of the organicsemiconductor film 404 was specified by a shadow mask. An evaporationmaterial was pentacene refined by sublimation. A film thickness of theorganic semiconductor film 404 was 150 nm.

FIG. 8 shows a state in which a source electrode 405 and a drainelectrode 406 were provided so as to be in contact with the organicsemiconductor film 404. The source electrode 405 and the drain electrode406 were formed using evaporation. Film formation regions of the sourceelectrode 405 and the drain electrode 406 were specified by a shadowmask. An evaporation material was Au. A film thickness of each of thesource electrode 405 and the drain electrode 406 was 100 nm.

The polishing condition was changed to produce substrates havingdifferent surface roughnesses Ra on the gate electrode. The substratewhich was processed up to the polishing step shown in FIG. 5 was cut toa card size (86 mm×54 mm). The surface roughness on the gate electrodewas evaluated by a scanning probe microscope (SPM) (produced by DigitalInstruments Inc.; product name: DI5000). The measurement was performedon five points within an area of 15 μm square in a tapping mode using ahigh aspect type probe tip AR5 (tip curvature radius was 10 nm to 15 nmand probe length was 2 μm). FIG. 2 shows an example of the surfaceroughness specified by the present invention, in which Ra is 3.8 nm.FIG. 2 is an atomic force microscope (AFM; scanning size: 15 μm) imageon the surface of the gate electrode. After the AFM measurement, stepsthat follow the step shown in FIG. 6 were performed on the substrate tocomplete a transistor device. After the completion, A DC characteristicof the transistor device was measured by a semiconductor parameteranalyzer (HP4155B). With respect to a pattern shape used for the test,120 transistor devices each having the same size were arranged on asingle substrate to be cut. As a result, a preferable transistorcharacteristic in which a gate leakage was small and a variation in Vthwas small was obtained.

On the other hand, FIG. 9 shows a comparative example to the presentinvention, in which the surface roughness Ra is 16.7 nm. FIG. 9 is anatomic force microscope (AFM; scanning size: 15 μm) image on the surfaceof the gate electrode in the comparative example. Similarly to theexample, the transistor characteristic was evaluated after the AFMmeasurement. As a result, it was observed that the gate leakage exceedsan allowable range in a large number of transistor devices.

With respect to transistor performance indexes, there are an on/offratio which is a ratio between a drain current Ion flowing when a switchis in an on state and a drain current Ioff flowing when a switch is inan off state (Ion/Ioff), a gate leakage indicating the insulationproperty of the gate insulating film, a cutoff frequency that followspulse drive, and the like. In this example, whether or not a transistordevice whose gate length was 50 μm and gate width was 3 mm has a goodquality was determined based on the following reference values.

(Evaluation Conditions)

On/off ratio: the on/off ratio was calculated by comparing draincurrents flowing when a gate voltage was changed between −20 V (onstate) and O V (off state) in a state in which a source voltage was 0 Vand a drain voltage was −20 V, and the transistor device was regarded asa defective product in the case where the calculated on/off ratio wassmaller than 500.

Gate leakage: in a state in which the gate voltage was 0 V, the sourcevoltage was 0 V, and the drain voltage was −20 V, the transistor devicewas regarded as a good quality product in the case where a gate currentwas equal to or smaller than 1 μA and transistor device was regarded asa defective product in the case where the gate current was larger than 1μA.

Table 1 shows an experimental result of an incidence of defectiveproducts, which was obtained using the above-mentioned evaluationmethod. As is apparent from Table 1, in the case of a sample in whichthe average surface roughness Ra specified by the present invention fellwithin a range of 0.1 nm to 15 nm, the incidence of defective productscould be suppressed. TABLE 1 Average surface Incidence of defectiveroughness Ra product (%) 0.1 to 1 nm 3 1 to 5 nm 5 5 to 10 nm 4 10 to 15nm 10 15 to 20 nm 25

EXAMPLE 2

An organic thin film transistor was produced as in Example 1 except thatpolyethylene terephthalate (PET) was used for the substrate and gold wasused for the gate electrode. With respect to the organic thin filmtransistor, a correlation between the average surface roughness Ra onthe surface of the gate electrode and the incidence of defectiveproducts was examined.

The used PET was an OHP film whose thickness was 0.1 mm and size was A4.This was cut to a card side (86 mm×54 mm) as in Example 1.

A gold thin film which was to become the gate electrode was formed usinga mask by resistance heating of tungsten boat in a vacuum evaporationsystem. In order to improve the contact of the gold thin film to thesubstrate, a thin chromium film was formed as a base layer. A thicknessof the gold thin film was 0.5 μm and a thickness of the chromium filmwas 0.1 μm.

Next, a laminate of the chromium film and the gold thin film which wasto become the gate electrode was polished by using a CMP. Samples inwhich the surface roughnesses were different from each other wereprepared by adjusting the polishing condition. The remaining steps wereperformed as in Example 1 to produce the thin film transistor device. Astatic characteristic of the produced device was measured by asemiconductor parameter analyzer. Table 2 shows a correlation betweenthe average surface roughness Ra and the incidence of defective productsof the organic thin film transistor. As is apparent from Table 2, in thecase of a sample in which the average surface roughness Ra specified bythe present invention fell within a range of 0.1 nm to 15 nm, theincidence of defective products could be suppressed. TABLE 2 Averagesurface Incidence of defective roughness Ra product (%) 0.1 to 1 nm 5 1to 5 nm 2 5 to 10 nm 8 10 to 15 nm 11 15 to 20 nm 31

When the organic thin film transistor was used for an integrated circuitin which a large number of transistors were formed, the incidence ofdefective products which was obtained in Example 1 and Example 2 was notnecessarily a sufficient level. This is probably because incidence ofdefective products is due not only to the above-mentioned gate leakagebut also to an experimental defect. Therefore, a difference between thecase where the average surface roughness Ra exceeds 15 nm and the casewhere it is equal to or smaller than 15 nm is seen as a clearsignificant difference.

EXAMPLE 3

A polyimide substrate having a thickness of 25 μm was used as theorganic substrate. A copper foil having a thickness of 25 μm was grownon the substrate by plating. Four substrates each having the growncopper foil were prepared.

The four substrates were subjected to four types of surface processings,which were no polishing, soft etching processing, polishing tapeprocessing, and CMP processing.

The conditions of the respective surface processing were as follows.

(Processing Conditions)

Soft etching processing: the substrate was immersed in 5% sulfuric acidfor 30 seconds and then washed using flowing deionized water for 2minutes. Tape processing: polishing tape (type: K8000); 60 second inpolishing time; 1 m/30 seconds in tape feed speed; and 2 kgf/cm² in rollpressure. CMP processing: Shibaura slurry CHS-3000EM; 5 kg in cylinderpressure; 80 rpm in the number of revolutions of retainer and platen;and 25 minutes in polishing time.

The respective substrates on which the above-mentioned processings wereperformed were cut to a size of 17 mm square. Then, a correlationbetween the average surface roughness Ra on the surface of the copperfoil and the insulation property of the insulating film formed on thesurface thereof was measured. NewView 5032 which was produced by ZygoCorporation was used for the measurement of the average surfaceroughness Ra. An objective lens of 10× magnification, of a Mirau opticalsystem was used for the measurement. A scan length was set to 5 μmbipolar. A measurement area size was 0.7 mm×0.53 mm.

The substrate which was measured was subjected to ultrasonic cleaningusing deionized water for 1 minute and acetone for 1 minute. After thecleaning, an Al₂O₃ film which was to become the gate insulating film wasformed on the substrate by a magnetron sputtering apparatus. The filmformation was performed by reactive sputtering in a mixture atmospherecontaining an Ar gas and an oxygen gas. A film formation pressure wasset to 0.5 Pa, applied power was set to 500 W at 13.56 MHz, and a filmthickness was set to 370 nm.

After the film formation, a gold film was formed as an upper electrodeon the substrate by evaporation using a mask. The mask was made of achromium film having a thickness of 40 μm, and 100 apertures, each ofwhich had 200 μm square were arranged in the mask at a pitch of 400 μm.A film thickness of the gold film was set to 120 nm.

With respect to each of the samples prepared through the above-mentionedprocessings, an insulation characteristic between the copper foil and anisolated gold pattern having 200 μm square was measured by asemiconductor parameter analyzer (HP4155B) produced by Hewlett-PackardDevelopment Company.

A leak current value caused at a time when a voltage of 0 V to 40 V wasapplied between Cu and Au was measured. When a value obtained bydividing a measurement value by an electrode area (current density)exceeded a preset value (1E-8 A/cm²) before the applied voltage reached40 V, the pattern was determined to be NG and the number of NG patternswere counted. The number of NG patterns was divided by the full numberof patterns to calculate an NG percentage (%).

FIG. 10 is a graph showing a measurement result in the case of nopolishing. Each line in the graph indicates the insulationcharacteristic between the gold pattern and the copper foil. Measurementresult values obtained at arbitrary 10 points are overlapped with oneanother on the graph. As a result, Ra was 197 nm, the NG percentage was100%, and an average current density at 40 V was 5.0×10⁻⁵ A/cm².

Similarly, FIG. 11 is a graph showing a measurement result in the caseof soft etching processing. Ra was 163 nm, the NG percentage was 85%,and an average current density at 40 V was 1.9×10⁻⁵ A/cm².

Similarly, FIG. 12 is a graph showing a measurement result in the caseof CMP polishing. Ra was 2 nm, the NG percentage was 6.8%, and anaverage current density at 40 V was 4.0×10⁻⁷ A/cm².

Similarly, FIG. 13 is a graph showing a measurement result in the caseof tape processing. Ra was 20 nm, the NG percentage was 100%, and anaverage current density at 40 V was 9.5×10⁻⁶ A/cm².

Similarly, FIG. 14 is a graph showing a measurement result in the caseof CMP polishing. Ra was 2 nm, the NG percentage was 2.2%, and anaverage current density at 40 V was 2.2×10⁻⁸ A/cm².

As is apparent from the above-mentioned results, the NG percentage is85% or more in the case of the sample in which Ra was equal to or largerthan 20 nm, but the NG percentage could be suppressed to be smaller than6.8% in the case of the CMP sample in which Ra is 2 nm.

EXAMPLE 4

Two different types of polyimide substrates each having a film thicknessof 25 μm were prepared as the organic substrates. With respect to thetwo types of used substrates, one was an A-substrate (produced by ToyoMetallizing Co., Ltd.; product name: Metaloyal FPC) and the other was aB-substrate (produced by UBE Industries, Ltd.; product name: UPISEL D).

A copper foil having a thickness of 0.3 μm was grown on each of thesubstrates by sputtering.

The above-mentioned respective substrates were cut to a size of 17 mmsquare. Then, the measurement of the surface roughness was performed.NewView 5032 produced by Zygo Corporation was used for the measurementof the surface roughness. An objective lens of 10× magnification, of aMirau optical system was used for the measurement. A scan length was setto 5 μm bipolar. A measurement area size was 0.7 mm×0.53 mm.

The substrate which was measured was subjected to ultrasonic cleaningusing deionized water for 1 minute and acetone for 1 minute. After thecleaning, an Al₂O₃ film which was to become the gate insulating film wasformed by the same process described in Example 3.

After the film formation, as in Example 3, a gold film was formed on thesubstrate by evaporation using a mask. The mask was made of a chromiumfilm having a thickness of 40 μm, and 100 apertures, each of which has200 μm square, were arranged in the mask at a pitch of 400 μm. A filmthickness of the gold film was set to 120 nm.

With respect to each of the samples of the A- and B-substrates whichwere prepared through the above-mentioned processings, an insulationcharacteristic between the copper foil and an isolated gold patternhaving 200 μm square was measured by a semiconductor parameter analyzer(HP4155B).

A leak current value caused at a time when a voltage of 0 V to 40 V wasapplied between Cu and Au was measured. When a value obtained bydividing a measurement value by an electrode area (current density)exceeded a preset value (1E-8 A/cm²) before the applied voltage reached40 V, the pattern was regarded as NG and the number of NG patterns wascounted. The NG percentage was calculated as in Example 3.

FIG. 15 is a graph showing a measurement result on the A-substrate. Rawas 20 nm, the NG percentage was 80%, and an average current density at40 V was 2.0×10⁻⁷ A/cm².

FIG. 16 is a graph showing a measurement result on the B-substrate. Rawas 15 nm, the NG percentage was 8%, and an average current density at40 V was 1.1×10⁻⁸ A/cm².

As is apparent from the above-mentioned results, the NG percentage was80% or more in the case of the A-substrate in which Ra was equal to orlarger than 20 nm but the NG percentage could be suppressed to besmaller than 8% in the case of the B-substrate in which Ra was 15 nm.

(Evaluation)

FIG. 17 is a graph showing a summary of the results in Example 3 andExample 4. The abscissa indicates the average surface roughness Ra andthe ordinate indicates the NG percentage. As is apparent from FIG. 17,when the average surface roughness Ra exceeds 15 nm, the NG percentagetends to significantly increase. It has been found that the range of theaverage surface roughness Ra (0.1 nm≦Ra≦15 nm) which was regarded aseffective by the present invention could be also applied to thesubstrate on which no polishing was performed. The gate leakage could bereduced, so that a yield in the case where the organic thin filmtransistor was produced could be improved.

(Production of Thin Film Transistor)

The thin film transistor was produced using the polyimide B-substrate(UPISEL D) in which the average surface roughness Ra was 15 nm. Alminahaving a thickness of 370 nm as in Example 3 was used for the gateinsulating film. The organic semiconductor film was made of pentacene.The source electrode and the drain electrode in the bottom structurewere made of a gold film having a film thickness of 500 nm. In anelement having a gate length of 50 μm and a gate width of 3 mm, apreferable characteristic such as the mobility of 0.15 cm²/Vs could beobtained under a condition in which a drain voltage was −20 V and a gatevoltage was −20 V.

The present invention has been described based on the structure shown inFIG. 1. However, the application of the present invention is not limitedto this structure. It can be easily understood by the person skilled inthe art that the present invention can be widely applied to a case thatfaces the same problem. In addition, it can be easily understood by theperson skilled in the art that parts which are not directly related tothe present invention, such as a field insulating film, a protectivefilm, and contact & via are significantly omitted in the description.

The present invention is not limited to the above embodiments andvarious changes and modifications can be made within the spirit andscope of the present invention. Therefore to apprise the public of thescope of the present invention, the following claims are made.

1. An organic thin film transistor comprising: an organic substrate; agate electrode; a gate insulating film; an organic semiconductor film; asource electrode; and a drain electrode, wherein an average surfaceroughness Ra of the gate electrode which is in contact with the gateinsulating film is 0.1 nm to 15 nm.
 2. The organic thin film transistoraccording to claim 1, wherein the organic substrate is made of one of aglass epoxy resin and polyethylene terephthalate.
 3. The organic thinfilm transistor according to claim 1, wherein the organic substrate ismade of polyimide.
 4. A method of manufacturing an organic thin filmtransistor comprising an organic substrate, a gate electrode, a gateinsulating film, an organic semiconductor film, a source electrode, anda drain electrode, the method comprising the step of: preparing anorganic substrate in which a planarized gate electrode is formed on asurface thereof; and forming a gate insulating film on the planarizedgate electrode, wherein an average surface roughness Ra of theplanarized gate electrode is 0.1 nm to 15 nm.
 5. The method ofmanufacturing an organic thin film transistor according to claim 4,wherein the organic substrate is made of one of a glass epoxy resin andpolyethylene terephthalate.
 6. The method of manufacturing an organicthin film transistor according to claim 4, wherein the organic substrateis made of polyimide.
 7. The method of manufacturing an organic thinfilm transistor according to claim 4, wherein the planarized gateelectrode is formed by sputtering.
 8. The method of manufacturing anorganic thin film transistor according to claim 4, further comprisingplanarizing the gate electrode.
 9. The method of manufacturing anorganic thin film transistor according to claim 8, wherein inplanarizing, at least one of chemical mechanical polishing (CMP), softetching, and polishing tape processing is performed.